The demand for high-speed, reliable electronic circuits and devices continues to grow at a rapid pace. Concurrently, the complexity of these circuits has also been increasing to meet the needs of a variety of applications. As the complexity and expense of these electronic circuits increases, the testing and analysis of the circuits for a variety of implementations also becomes increasingly important. In addition, accessing certain elements of these circuits has also become more difficult as the elements themselves are scaled smaller and as circuits are formed in increasingly dense arrangements.
Boundary scan analysis is one type of approach used for testing and analyzing circuits, and has been found particularly useful for applications where access to circuit elements for testing is limited. Boundary scan analysis is a methodology allowing controllability and observability of boundary pins of a Joint Test Access Group (JTAG) compatible device via software control. The analysis is typically implemented using the Institute of Electrical and Electronic Engineers (IEEE) standard 1149.1, known as the IEEE Standard Test Access Port and Boundary Scan Architecture. Circuits arranged for boundary-scan analysis typically employ built-in architecture, with pins located at the “boundary” of the circuit and accessible for passing test signals to and from the circuit. Inputs provided via the pins are coupled to various portions of the circuit, depending on the type of input. Outputs from the circuit are passed to external test circuitry via the pins.
The boundary-scan test architecture provides a means to test interconnects between integrated circuits on a board without necessarily using physical test probes, and can be implemented using a variety of circuits. In most applications, a boundary-scan cell that includes a multiplexer and latches is coupled to each pin on the device. These boundary-scan cells capture data from pin or core logic signals, or force data onto pins. Captured data is serially shifted out via the pins for analysis (e.g., externally compared to expected results). Forced test data is serially shifted into the boundary-scan cells via the data port input pins. The shifting and other boundary-scan operations are controlled, for example, using a serial data path (e.g., a scan path or scan chain).
By allowing direct access to nets, boundary-scan eliminates the need for large numbers of test vectors that are normally needed to properly initialize sequential logic. Tens or hundreds of vectors may do the job that had previously required thousands of vectors. Potential benefits realized from the use of boundary-scan are shorter test times, higher test coverage, increased diagnostic capability and lower capital equipment cost.
BSDL facilitates the description of testability features in components that comply with IEEE Standard 1149, discussed above. This language can be used by tools that make use of those testability features. With a BSDL description of a component and knowledge of IEEE Standard 1149, it is possible to describe data transport characteristics of a particular component that relate to the capture, shifting and updating of data in a particular IC.
While boundary scan analysis has been found very useful, certain aspects thereof have presented challenges. For example, boundary scan analysis relies on programming language (i.e., boundary scan description language (BSDL)) for operational instructions. However, in some applications, the construction of a correct BSDL file is difficult due to a large number of inputs and outputs and very specific device architecture. Approaches that have previously been used to construct BSDL have typically been unreliable insofar as they depend upon the correct interpretation of relevant device information. For instance, text editor approaches, BSDL editor approaches and synthesis methods that create BSDL files from computer aided engineering (CAE) design data have all exhibited suspect reliability. In addition, automatic analysis methods based upon specific register-transfer level (RTL) description of boundary scan chains or on unmodified or annotated schematics typically fail to address extended circuit features or complex cell designs.
The present invention may address one or more of the above issues.